The present invention relates to a printhead substrate for inputting a data signal in synchronization with a clock signal, printhead, printhead cartridge, and printer thereof.
FIGS. 1 and 2 show respectively a layout and a circuit diagram of a conventional inkjet printhead for inputting a data signal in synchronization with a clock signal.
Referring to FIG. 1, a printhead substrate (heater board) 100 includes: a heater portion 101 serving as an electrothermal transducer; a driver portion 102 having a transistor for driving the heater portion 101; a latch 103 latching printing data; a shift register 104 storing serially inputted printing data; and a PAD portion 105 serving as an input terminal where various signals are inputted.
FIG. 2 is a circuit diagram of the heater board 100 shown in FIG. 1. Components common to those shown in FIG. 1 are referred to by the same reference numerals. The heater portion 101 includes a plurality of heaters (resisters) and the driver portion 102 has an FET transistor, a buffer circuit for each heater.
FIG. 3 is a view explaining a relation between input waveforms, obtained when the CLK signal and DATA signal driving the circuit shown in FIG. 2 are inputted to the heater board 100, and input waveforms obtained when the CLK signal and DATA signal are inputted to the points A and B of the shift register 104.
Assume herein that the DATA signal is inputted to the shift register 104 in synchronism with two transitional states (leading and trailing edge) of CLK signals, i.e., a state changing from a low level to a high level, and a state changing from a high level to a low level. Note that the DATA signal, sent from a printer main unit employing the printhead, is a high-level or low-level signal for turning on/off a desired heater (heating element). The DATA signal inputted to the PAD portion 105 is sent to the Schmitt circuit 106, then through the buffer circuit 107 connected to the output terminal of the Schmitt circuit 106, inputted to the shift register 104 (point B). Similarly, the CLK signal from the PAD portion 105 is inputted to the Schmitt circuit 106, then through the buffer circuit 107 connected to the output terminal of the Schmitt circuit 106, inputted to the shift register 104 (point A). The DATA signal is inputted to the shift register 104 in synchronization with both transitions of a low level to a high level and a high level to a low level of the CLK signal.
In a case where the number of shift registers 104 provided is one as in a conventional printhead, the number of logic gates from the PAD portion 105 to the shift register 104 is equal in the CLK signal and DATA signal. Furthermore, a load driven by each of the buffer circuits 107 is equal in the CLK signal and DATA signal. Therefore, the time lag of the CLK signal generated between the PAD portion 105 and the point A is equal to the time lag of the DATA signal generated between the PAD portion 105 and the point B. Thus, the temporal relative relation between the CLK signal and DATA signal is equal in the PAD portion 105 and the input portions A and B of the shift register 104. In order to surely input the DATA signal to the shift register 104 without malfunction, the level of the DATA signal needs to be constant before and after the transition of the CLK signal. In other words, the time during which the DATA signal is constant with respect to the CLK signal, i.e., setup time and hold time, must be equal in the input portions A and B of the shift register 104 so as to allow a margin for malfunction and enable high-speed data transfer.
In order to meet the recent demands for high-precision printing quality of a color image, for instance as shown in FIG. 4, a single heater board (head substrate) comprises plural heating elements (heaters) for printing images in plural colors. Furthermore, in keeping with the trend of increasing speed and higher precision in printing, a discharge frequency of the heaters is increased with increasing of the number of heaters. As a result, the amount of data transferred to the printhead per unit time increases. In order to handle the increased amount of data, the transferred data is divided, and the divided plural blocks of data are transferred simultaneously in synchronization with one clock signal. In this case, a plurality of shift registers need to be provided in the printhead in conformity to the plural blocks of data.
In the printhead having a plurality of shift registers, in order to simultaneously input the DATA signal to the plurality of shift registers in synchronization with the clock signal, it is necessary to input a number of CLK signals and DATA signals corresponding to the number of shift registers. However, if a plurality of pads for inputting these signals and corresponding input circuits are provided in the printhead substrate, the layout area necessary for these circuits increases, and as a result, the chip size increases. Furthermore, since the aforementioned substrate is formed on a silicon wafer, the increased chip size causes a decreased number of chips produced from one sheet of wafer, resulting in an increased cost.
In order to avoid the increased chip size, it is necessary to reduce the number of signal lines inputted to the heater board. To realize this, the CLK signal serving as a common synchronization signal for the plural shift registers 401 to 406 is provided as a common signal so that, for instance, only one input pad is necessary for the CLK signal as shown in FIG. 5. In this case, while plural shift registers 401 to 406 are connected to the output of the buffer circuit 500 of the CLK signal, only one shift register is connected to each output of the buffer circuit 501 of the DATA signal. Assuming that a current driving capability of the buffer circuit 500 is equal to that of the buffer circuit 501, a difference is generated between a time lag of the CLK signal and a time lag of the DATA signal inputted to each shift register. More specifically, there is more delay in the CLK signal than the DATA signal. When a power-supply voltage is 5V as in a conventional case, the time lag of the signal is small since the current driving capability of the buffer circuit 500 is sufficient. Therefore, the difference between the time lag of the CLK signal and the time lag of the DATA signal is small in each shift register.
For an interface of a conventional printer, a parallel interface has been employed in general. In this case, a power-supply voltage used for the logic of the printer main unit is 5V. Also, a power-supply voltage for the logic of an inkjet printhead substrate in the head is 5V. Furthermore, a part of an IC of the printer""s internal circuit requires a 5V power supply. These are the background of the feature of the inkjet printhead substrate, which has been developed to use a 5V logic power supply.
However, recently as the microtechnology of an IC design rule has improved and a new interface has been employed, adopting a 5V logic power supply is disadvantageous in terms of cost and size. In view of this, adopting 3.3V is the recent movement in the mainstream of a logic power supply of a printer main unit. However, it has been confirmed that several problems occur if a logic power-supply voltage in a head substrate is lowered from the time-proven 5V to 3.3V. The problems are described below with reference to drawings.
One of the problems is reduced image data transfer capability of an inkjet printhead substrate.
FIG. 18 shows an example of a construction of an inkjet printhead substrate. Reference numeral 1003 denotes a pad receiving a signal from an external unit. A VDD terminal 1006 receives a logic power-supply voltage, a VH terminal 1008 receiving a heater driving power-supply voltage, a GND terminal 1005 connected to a ground, and a VSS terminal 1007. Furthermore, a logic circuit 1002, such as a shift register, which serially receives image data and outputs the image data in parallel, a driver portion 1001 driving each heater 1004 and so on are provided in one silicon substrate.
FIG. 19 shows further in detail a case where the heaters 1004 are provided for 620 dots (bits). The heaters for 620 bits are divided into 16 blocks, each for 40 bits. The heaters for up to 40 bits are driven simultaneously in block unit. By repeating the driving of the heaters for 16 times, all the heaters for 620 bits are driven (correspond to 1 cycle). FIG. 20 shows driving timing of the heaters. Hereinafter a description is provided on image data transfer speed necessary to drive all the heaters for 620 bits at a driving frequency of 15 KHz that is required for one line unit, in a case where constant high-speed printing is performed.
A clock cycle of the driving frequency 15 KHz is 66.67 xcexcs. The 40-bit image data transfer must be performed for 16 time divisions (blocks) within the given time. A frequency necessary for the CLK signal, which transfers the image data signal DATA, is at least 12 MHz or more. Although this frequency is not much of a fast value taking a process speed of a general CPU into consideration, in the case of an inkjet printhead, 12 MHz is not easy to achieve because a running carriage and a main body are connected with a long flexible substrate or the like and there is a need for a small carriage due to downsizing of a printer.
Keeping these circumstances in mind, a description is now provided with reference to FIGS. 21A and 21B on a reduced data transfer capability in a case where the logic power-supply voltage is lowered from 5V to 3.3V.
FIG. 21A shows a logic signal (power supply) voltage and a maximum CLK frequency at which image data is transferable.
As shown in FIG. 21A, as the logic signal (power-supply) voltage decreases, the CLK frequency tends to decrease. This is due to the fact that the decreased logic power-supply voltage used as a gate voltage of a CMOS causes a decline in the driving capability of a MOS transistor employed in the shift register or the input circuit of the CLK or the like for transferring image data.
Furthermore, in the inkjet printhead substrate, the heaters on the substrate must be driven to achieve satisfactory speed while taking the temperature into consideration. This is a capability characteristically required for an inkjet printhead substrate, which discharges ink by heating ink with heaters. FIG. 21B shows a relation between a temperature on a substrate and maximum CLK frequency. The graph shows the tendency of reduction in data transfer capability as the logic voltage is lowered to 3.3V, and tendency of reduction in data transfer capability as the temperature rises.
As can be understood from the above description, although 5V logic voltage has caused no problem at 12 MHz CLK frequency, lowering the logic voltage to 3.3V requires an increased data transfer capability.
Next, a description is provided on factors of the reduced data transfer capability caused by an enlarged difference between a time lag of the CLK signal and a time lag of the DATA signal in the head substrate due to the aforementioned lowered logic voltage.
Along with the lowered logic voltage, a gate voltage driving the MOS transistor constructing the logic circuit also declines. FIG. 6 shows how a drain current (Id) depends upon a drain-source voltage (Vds) when a gate voltage Vgs of the MOS transistor is used as a parameter. As is apparent from FIG. 6, when the gate voltage Vgs is lowered from 5V to 3.3V, the current driving capability becomes xc2xd or lower.
Furthermore, in a case where a CMOS inverter drives the gate of the MOS transistor, it can be said that a load corresponding to a capacitance of an equivalently driving gate is given to an output of the inverter as shown in FIG. 7. Assuming that an on-resistance of the MOS is RMOS and an equivalent load capacitance is Cgate, a time constant from the time an input of the inverter changes till the time an output of the MOS transistor is inverted is expressed by Cgatexc3x97RMOS. If the load is unchanged and the value of RMOS becomes doubled or higher due to the lowered voltage, the time constant also becomes twice as high or higher.
Referring back to FIG. 4, assume that a capacitance of an input of the CLK signal is equal (CL) to a capacitance of an input signal of the DATA signal in one shift register, an on-resistance at the time of driving the buffer circuit 500 is RBUF, and the number of shift registers is n. The time lag generated between the signal input in the buffer circuit and signal input in the shift register is proportional to (CLxc3x97RBUF) in the DATA signal, while it is proportional to (nxc3x97CLxc3x97RBUF) in the CLK signal. Furthermore, because the time lags of the DATA signal and CLK signal become n times as long and the on-resistance value at the time of driving the buffer circuit becomes doubled due to the lowered logic power-supply voltage, the difference in the time lag is twice as much as the conventional difference. Therefore, the time lag cannot be disregarded.
FIG. 8 shows signal waveforms in a case the CLK signal is delayed with respect to the DATA signal in the input of each shift register. The upper side of FIG. 8 shows waveforms of respective signals inputted to the input pad, and the lower side of FIG. 8 shows waveforms of signals inputted to each shift register. While the setup time and hold time, serving as a margin of the DATA signal with respect to the CLK signal in the input pad are substantially equal in the upper side of FIG. 8, in the input portion of the shift register, the margin of a time difference (hold time) 801 between the transition timing of the CLK signal and changing timing of the DATA signal is reduced because the time lag of the CLK signal is larger than the time lag of the DATA signal.
In the above-described manner, because the margin of the setup time or hold time at the time of shift register input is reduced, it becomes difficult to ensure inputting of a data signal to the shift register. This becomes the cause of malfunction, and makes it difficult to realize high-speed data transfer with an increased frequency of CLK signal.
Furthermore, although the above descriptions have been provided on a case of a printhead substrate having plural shift registers, along with the tendency to have a multi-bit printhead and a reduced chip size, wirings for the DATA signal and CLK signal tend to be longer inside the chip. As a result, a parasitic capacitance and resistance value in wirings of the CLK signal and DATA signal increase, causing a large difference in the parasitic components in the wirings of the DATA signal and CLK signal. Even if the number of shift registers connected to the DATA signal and CLK signal is equal, when the parasitic capacitance and resistance value in the wirings of the output of the buffer are different in the DATA signal and CLK signal, a large difference is generated between the time lag of the DATA signal and the time lag of the CLK signal inputted to each shift register due to the lowered power-supply voltage, as similar to the above-described case. This becomes the cause of malfunction and interferes with high-speed data transfer.
The present invention has been proposed in view of the above-described conventional examples, and has as its object to reduce a difference between a time lag of a data signal and a time lag of a clock signal, which is caused by a lowered voltage of a logic power-supply, in order to ensure setup time and hold time of the clock signal and data signal inputted to each register, thereby providing a printhead substrate, printhead, printhead cartridge, and printer, accommodated to high-speed data transfer without increasing a manufacturing cost.
In order to attain the above described objects, a printhead substrate of the present invention comprises the structure as follows:
A printhead substrate inputting a data signal in synchronization with a clock signal, comprises: a plurality of printing elements; input terminals adapted to input the clock signal and data signal; a register adapted to input the clock signal and data signal inputted from said input terminals, and maintain the data signal in synchronization with the clock signal; a time lag adjusting circuit adapted to be arranged between at least one of said input terminals and an input terminal of said register to adjust a time lag of at least one of the clock signal or data signal; and a driver circuit adapted to drive said plurality of printing elements based on the data signal, wherein adjusting the time lag by said time lag adjusting circuit ensures setup time and hold time between the clock signal and the data signal inputted to said register from the input terminals.
In order to attain the above described objects, a printhead of the present invention comprises the structure as follows:
A printhead comprising: a plurality of printing elements; input terminals adapted to input a clock signal and a data signal; a register adapted to input the clock signal and data signal inputted from said input terminals, and maintain the data signal in synchronization with the clock signal; a time lag adjusting circuit adapted to be arranged between at least one of the input terminals and an input terminal of said register to adjust a time lag of at least one of the clock signal or data signal; and a driver circuit adapted to drive said plurality of printing elements based on the data signal, wherein adjusting the time lag by said time lag adjusting circuit ensures setup time and hold time between the clock signal and the data signal inputted to said register from the input terminals.
Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof.